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168 pin DRAM (Unbuffered) 168 PIN DIMM at the computer

Front Side (left side 1-42, right side 43-84)
Back Side (left side 85-126, right side 127-168)

Front, Left

Pin
Non-Parity?
Parity?
72 ECC?
80 ECC?
Description
1
VSS
VSS
VSS
VSS
Ground
2
DQ0
DQ0
DQ0
DQ0
Data 0
3
DQ1
DQ1
DQ1
DQ1
Data 1
4
DQ2
DQ2
DQ2
DQ2
Data 2
5
DQ3
DQ3
DQ3
DQ3
Data 3
6
VCC
VCC
VCC
VCC
+5 VDC or +3.3 VDC
7
DQ4
DQ4
DQ4
DQ4
Data 4
8
DQ5
DQ5
DQ5
DQ5
Data 5
9
DQ6
DQ6
DQ6
DQ6
Data 6
10
DQ7
DQ7
DQ7
DQ7
Data 7
11
DQ8
DQ8
DQ8
DQ8
Data 8
12
VSS
VSS
VSS
VSS
Ground
13
DQ9
DQ9
DQ9
DQ9
Data 9
14
DQ10
DQ10
DQ10
DQ10
Data 10
15
DQ11
DQ11
DQ11
DQ11
Data 11
16
DQ12
DQ12
DQ12
DQ12
Data 12
17
DQ13
DQ13
DQ13
DQ13
Data 13
18
VCC
VCC
VCC
VCC
+5 VDC or +3.3 VDC
19
DQ14
DQ14
DQ14
DQ14
Data 14
20
DQ15
DQ15
DQ15
DQ15
Data 15
21
n/c
CB0
CB0
CB0
Parity/Check Bit Input/Output 0
22
n/c
CB1
CB1
CB1
Parity/Check Bit Input/Output 1
23
VSS
VSS
VSS
VSS
Ground
24
n/c
n/c
n/c
CB8
Parity/Check Bit Input/Output 8
25
n/c
n/c
n/c
CB9
Parity/Check Bit Input/Output 9
26
VCC
VCC
VCC
VCC
+5 VDC or +3.3 VDC
27
/WE0
/WE0
/WE0
/WE0
Read/Write Input
28
/CAS0
/CAS0
/CAS0
/CAS0
Column Address Strobe 0
29
/CAS1
/CAS1
/CAS1
/CAS1
Column Address Strobe 1
30
/RAS0
/RAS0
/RAS0
/RAS0
Row Address Strobe 0
31
/OE0
/OE0
/OE0
/OE0
Output Enable
32
VSS
VSS
VSS
VSS
Ground
33
A0
A0
A0
A0
Address 0
34
A2
A2
A2
A2
Address 2
35
A4
A4
A4
A4
Address 4
36
A6
A6
A6
A6
Address 6
37
A8
A8
A8
A8
Address 8
38
A10
A10
A10
A10
Address 10
39
A12
A12
A12
A12
Address 12
40
VCC
VCC
VCC
VCC
+5 VDC or +3.3 VDC
41
VCC
VCC
VCC
VCC
+5 VDC or +3.3 VDC
42
DU
DU
DU
DU
Don't Use

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